fast parallel algorithms for binary multiplication and their implementation on systolic architecture

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dc.contributor.authorSinha, Bhabani P
dc.contributor.authorSrimani, Pradip K
dc.date.accessioned2012-07-25T07:32:34Z
dc.date.available2012-07-25T07:32:34Z
dc.date.issued1989
dc.identifier.citationIEEE transaction on computers,V38,3,P424-431en_US
dc.identifier.urihttp://hdl.handle.net/10263/4466
dc.language.isoenen_US
dc.subjectParallel algorithmen_US
dc.subjectBinary multiplicationen_US
dc.titlefast parallel algorithms for binary multiplication and their implementation on systolic architectureen_US
dc.typeArticleen_US

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