A unified approach to topology generation and optimal sizing of floorplans
| dc.contributor.author | Dasgupta, Partha Sarathi | |
| dc.contributor.author | Sur Kolay, Susmita | |
| dc.contributor.author | Bhattacharya, Bhargab B | |
| dc.date.accessioned | 2012-10-19T09:46:54Z | |
| dc.date.available | 2012-10-19T09:46:54Z | |
| dc.date.issued | 1998-09 | |
| dc.identifier.citation | IEEE Transactions on computer -Aided Design of Integrated Circuits and Systems,v.17,no.2,p.126-135 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10263/4552 | |
| dc.language.iso | en | en_US |
| dc.subject | AND-OR graph search | en_US |
| dc.subject | VLSI floorplaning | en_US |
| dc.title | A unified approach to topology generation and optimal sizing of floorplans | en_US |
| dc.type | Article | en_US |
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