A pipeline architecture for computing the euler number of a binary image

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dc.contributor.authorBishnu, A
dc.contributor.authorBhattacharya, Bhargab B
dc.contributor.authorKundu, Malay K
dc.contributor.authorMurthy, C A
dc.contributor.authorAcharya, Tinku
dc.date.accessioned2012-01-04T14:22:42Z
dc.date.available2012-01-04T14:22:42Z
dc.date.issued2005
dc.identifier.citationJournal of system acrhitecture,V51,P470-487en_US
dc.identifier.urihttp://hdl.handle.net/10263/2824
dc.language.isoenen_US
dc.subjectEuler numberen_US
dc.subjectImage processingen_US
dc.subjectPipeline architectureen_US
dc.subjectVLSI implementationen_US
dc.titleA pipeline architecture for computing the euler number of a binary imageen_US
dc.typeArticleen_US

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