Fast Parallel algorithm for ternary multiplication using multivariate I L technology

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Binder2.pdf (968.58 KB)

Date

1994

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Description

Keywords

Balanced ternary logic, Coloum compression, Ternary multiplication, Systolic architecture

Citation

IEEE transaction of computors,V43,P603-607

URI

http://hdl.handle.net/10263/4373

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Electronics

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