Hierarchical partitioning of VLSI floorplans by staircases

Simple item page
dc.contributor.authorMajumder, S
dc.contributor.authorSur Kolay, Susmita
dc.contributor.authorBhattacharya, Bhargab B
dc.contributor.authorDas, S K
dc.date.accessioned2011-09-19T11:13:59Z
dc.date.available2011-09-19T11:13:59Z
dc.date.issued2007
dc.identifier.citationACM Transactions on design automation of electronic systemsV12,P141-159en_US
dc.identifier.urihttp://hdl.handle.net/10263/2574
dc.language.isoenen_US
dc.subjectFloorplanningen_US
dc.subjectGlobal routingen_US
dc.subjectNetwork flowen_US
dc.subjectN P completenessen_US
dc.subjectBalanced bipartitioningen_US
dc.titleHierarchical partitioning of VLSI floorplans by staircasesen_US
dc.typeArticleen_US

Files

Original bundle

Now showing 1 - 1 of 1
No Thumbnail Available
Name:
hierarchical partitioning.pdf
Size:
2.92 MB
Format:
Adobe Portable Document Format
Download

License bundle

Now showing 1 - 1 of 1
No Thumbnail Available
Name:
license.txt
Size:
1.71 KB
Format:
Item-specific license agreed upon to submission
Description:
Download

Collections

Mathematics and Statistics