Fast parallel algorithm for ternary multiplication using multivalued IL technology

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dc.contributor.authorDe, Mallika
dc.contributor.authorSinha, Bhabani P
dc.date.accessioned2013-05-07T12:09:41Z
dc.date.available2013-05-07T12:09:41Z
dc.date.issued1994-05
dc.identifier.citationIEEETOC, v 43, no 5, p 603-607en_US
dc.identifier.urihttp://hdl.handle.net/10263/5351
dc.language.isoenen_US
dc.subjectBalanced ternary logicen_US
dc.subjectColumn compressionen_US
dc.subjectPrecarry additionen_US
dc.subjectSystolic architectureen_US
dc.subjectTernary multiplicationen_US
dc.titleFast parallel algorithm for ternary multiplication using multivalued IL technologyen_US
dc.typeArticleen_US

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