Fast parallel algorithm for ternary multiplication using multivalued IL technology

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Fast parallel algorithm for ternary multiplication using multivalued IL technology-IEEETOC-43-5-1994 .pdf (1.04 MB)

Date

1994-05

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Keywords

Balanced ternary logic, Column compression, Precarry addition, Systolic architecture, Ternary multiplication

Citation

IEEETOC, v 43, no 5, p 603-607

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http://hdl.handle.net/10263/5351

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Computer Science

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