Parallel system design for time- delay neural networks

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dc.contributor.authorZhang, David
dc.contributor.authorPal, Sankar K
dc.date.accessioned2013-03-04T12:22:54Z
dc.date.available2013-03-04T12:22:54Z
dc.date.issued2000
dc.identifier.citationIEEETOSMAC, v 30, no 2, p 265-275en_US
dc.identifier.urihttp://hdl.handle.net/10263/5339
dc.language.isoenen_US
dc.subjectParallel computingen_US
dc.subjectPipelined architectureen_US
dc.subjectTime- delay neural networksen_US
dc.subjectSpeech recognitionen_US
dc.titleParallel system design for time- delay neural networksen_US
dc.typeArticleen_US

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