Design of parity testable combinational circuits

Simple item page
dc.contributor.authorBhattacharya, Bhargab B
dc.date.accessioned2013-06-14T12:29:13Z
dc.date.available2013-06-14T12:29:13Z
dc.date.issued1989
dc.identifier.citationIEEE Transactions on Computers,v.38 ,no.11 ,p.1580-1584en_US
dc.identifier.urihttp://hdl.handle.net/10263/5433
dc.language.isoenen_US
dc.subjectParity testableen_US
dc.subjectCombinational circuiten_US
dc.subjectMaximal supergatesen_US
dc.subjectSingle external test-mode pinen_US
dc.titleDesign of parity testable combinational circuitsen_US
dc.typeArticleen_US

Files

Original bundle

Now showing 1 - 1 of 1
No Thumbnail Available
Name:
ITOC-38-11-1989-P1580-1584.pdf
Size:
400.29 KB
Format:
Adobe Portable Document Format
Download

License bundle

Now showing 1 - 1 of 1
No Thumbnail Available
Name:
license.txt
Size:
1.71 KB
Format:
Item-specific license agreed upon to submission
Description:
Download

Collections

Computer Science