Partial reconfiguration of field programmable gate array devices using xilinx architecture
| dc.contributor.author | Roy Chowdhury, Ayan | |
| dc.date.accessioned | 2016-07-06T16:40:35Z | |
| dc.date.available | 2016-07-06T16:40:35Z | |
| dc.date.issued | 2007 | |
| dc.description | Dissertation under the supervision of Dr. Susmita Sur-Koley | en_US |
| dc.identifier.citation | 41p. | en_US |
| dc.identifier.uri | http://hdl.handle.net/10263/6366 | |
| dc.language.iso | en | en_US |
| dc.publisher | Indian Statistical Institute, Kolkata | en_US |
| dc.relation.ispartofseries | Dissertation;2007-203 | |
| dc.subject | FPGA | en_US |
| dc.subject | Partitioner | en_US |
| dc.subject | Algorithms | en_US |
| dc.subject | Dynamic reconfiguration | en_US |
| dc.subject | Partial reconfiguration | en_US |
| dc.subject | Xilinx architecture | en_US |
| dc.title | Partial reconfiguration of field programmable gate array devices using xilinx architecture | en_US |
| dc.type | Thesis | en_US |
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