Logic design using digital summarion threshold-logic gates

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dc.contributor.authorPal, A
dc.date.accessioned2014-06-13T09:40:24Z
dc.date.available2014-06-13T09:40:24Z
dc.date.issued1983
dc.identifier.citationIEE Proceedings, V.130. No.1, P 32-36en_US
dc.identifier.urihttp://hdl.handle.net/10263/5918
dc.language.isoenen_US
dc.subjectLogic designen_US
dc.subjectDigital summationen_US
dc.subjectAlgorithmsen_US
dc.subjectSystemen_US
dc.titleLogic design using digital summarion threshold-logic gatesen_US
dc.typeArticleen_US

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